[PATCH] D59758: [DAGCombiner] Combine OR as ADD when no common bits are set

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope updated this revision to Diff 193124.
bjope added a comment.

Added extra test in test/CodeGen/X86/signbit-shift.ll to show that add_zext_ifpos_vec_splat only turn up as a regression due to register contraints.

The new add_zext_ifpos_vec_splat2 show an improvement since we get

pcmpeqd	%xmm0, %xmm0
	pcmpgtd	%xmm0, %xmm1
	movdqa	.LCPI3_0(%rip), %xmm0   # xmm0 = [42,42,42,42]
	psubd	%xmm1, %xmm0

instead of

movdqa	%xmm1, %xmm0
	pcmpeqd	%xmm1, %xmm1
	pcmpgtd	%xmm1, %xmm0
	psrld	$31, %xmm0
	por	.LCPI3_0(%rip), %xmm0


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59758/new/

https://reviews.llvm.org/D59758

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AMDGPU/calling-conventions.ll
  llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
  llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
  llvm/test/CodeGen/Hexagon/subi-asl.ll
  llvm/test/CodeGen/X86/scheduler-backtracking.ll
  llvm/test/CodeGen/X86/signbit-shift.ll
  llvm/test/CodeGen/X86/split-store.ll

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