[PATCH] D60041: [X86] Merge the different CMOV instructions for each condition code into single instructions that store the condition code as an immediate.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.
Herald added subscribers: jdoerfert, lebedev.ri, kristina.
Herald added a reviewer: lebedev.ri.
Herald added a project: LLVM.

Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models.

This avoids needing an isel pattern for each condition code. And it removes
translation switches for converting between CMOV instructions and condition
codes.

Now the printer, encoder and disassembler take care of converting the immediate.
We use InstAliases to handle the assembly matching. But we print using the
asm string in the instruction definition. The instruction itself is marked
IsCodeGenOnly=1 to hide it from the assembly parser.

This does complicate the scheduler models a little since we can't assign the
A and BE instructions to a separate class now.

I plan to make similar changes for SETcc and Jcc.


Repository:
  rL LLVM

https://reviews.llvm.org/D60041

Files:
  include/llvm/Support/X86DisassemblerDecoderCommon.h
  lib/Target/X86/Disassembler/X86Disassembler.cpp
  lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
  lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp
  lib/Target/X86/InstPrinter/X86InstPrinterCommon.h
  lib/Target/X86/MCTargetDesc/X86BaseInfo.h
  lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  lib/Target/X86/X86CmovConversion.cpp
  lib/Target/X86/X86FastISel.cpp
  lib/Target/X86/X86FlagsCopyLowering.cpp
  lib/Target/X86/X86FrameLowering.cpp
  lib/Target/X86/X86ISelDAGToDAG.cpp
  lib/Target/X86/X86InstrCMovSetCC.td
  lib/Target/X86/X86InstrCompiler.td
  lib/Target/X86/X86InstrFoldTables.cpp
  lib/Target/X86/X86InstrFormats.td
  lib/Target/X86/X86InstrInfo.cpp
  lib/Target/X86/X86InstrInfo.h
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86SchedBroadwell.td
  lib/Target/X86/X86SchedHaswell.td
  lib/Target/X86/X86SchedPredicates.td
  lib/Target/X86/X86SchedSandyBridge.td
  lib/Target/X86/X86SchedSkylakeClient.td
  lib/Target/X86/X86SchedSkylakeServer.td
  lib/Target/X86/X86Schedule.td
  lib/Target/X86/X86ScheduleAtom.td
  lib/Target/X86/X86ScheduleBdVer2.td
  lib/Target/X86/X86ScheduleBtVer2.td
  lib/Target/X86/X86ScheduleSLM.td
  lib/Target/X86/X86ScheduleZnver1.td
  lib/Target/X86/X86SpeculativeLoadHardening.cpp
  test/CodeGen/X86/flags-copy-lowering.mir
  test/CodeGen/X86/non-value-mem-operand.mir
  test/CodeGen/X86/post-ra-sched-with-debug.mir
  test/CodeGen/X86/tail-call-conditional.mir
  unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
  utils/TableGen/X86RecognizableInstr.cpp
  utils/TableGen/X86RecognizableInstr.h

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