[PATCH] D59952: [VPLAN] Remove option for stress testing.

[Hideki Saito via Phabricator via llvm-commits]

hsaito added inline comments.


================
Comment at: lib/Transforms/Vectorize/LoopVectorize.cpp:6106
-      else
-        VF = determineVPlanVF(TTI->getRegisterBitWidth(true /* Vector*/), CM);
-    }
----------------
If we are removing stress testing, I'd like to make sure that, there is a mode where we always get VF > 1. Vectorizing for AVX2 almost fits the profile (double complex is 128bit, YMM register is 256bit), but at Intel, we don't want to stop at just thinking about POD types.

If that is not the case, there is a value in stress testing, at least until we become confident that VPlan vectorizer can handle all cases of OpenMP simd and declare simd. Helps our development.




Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59952/new/

https://reviews.llvm.org/D59952