[PATCH] D59799: [wip][mips] Use AltOrders to prevent using odd FP-registers

[Simon Dardis via Phabricator via llvm-commits]

sdardis added a comment.

My initial comments are that this looks ok, but I would like a longer look at it.



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Comment at: llvm/lib/Target/Mips/MipsRegisterInfo.td:385
 // * FGR32 - 32 32-bit registers (single float only mode)
-def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
+def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)> {
+  let AltOrders = [(sub FGR32, (decimate (sequence "F%u", 1, 31), 2))];
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Nit: Can you provide a comment summarising the reason for the AltOrder additions?


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Comment at: llvm/lib/Target/Mips/MipsRegisterInfo.td:394
 def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
-             Unallocatable;
+             Unallocatable {
+  let AltOrders = [(sub FGRH32, (decimate (sequence "F_HI%u", 1, 31), 2))];
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To the best of my knowledge, the FGRH32 regclass is unused. I did remove it locally and run the test-suite, and as best I can recall it made no difference but I didn't run all configurations.

Dealing with that would be a separate commit.


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Comment at: llvm/lib/Target/Mips/MipsRegisterInfo.td:414
 
-def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
-
-// Used to reserve odd registers when given -mattr=+nooddspreg
-// FIXME: Remove double precision registers from this set.
-def OddSP : RegisterClass<"Mips", [f32], 32,
-                          (add (decimate (sequence "F%u", 1, 31), 2),
-                               (decimate (sequence "F_HI%u", 1, 31), 2),
-                               (decimate (sequence "D%u", 1, 15), 2),
-                               (decimate (sequence "D%u_64", 1, 31), 2))>,
-            Unallocatable;
+def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> {
+  let AltOrders = [(sub FGR64, (decimate (sequence "D%u_64", 1, 31), 2))];
----------------
Nit: Can you provide a comment summarising the reason for the AltOrder additions?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D59799/new/

https://reviews.llvm.org/D59799