[PATCH] D59853: MIR: Freeze reserved regs after parsing everything

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: thegameg.
Herald added subscribers: tpr, nhaehnle, wdng, jvesely.

The AMDGPU implementation of getReservedRegs depends on
MachineFunctionInfo fields that are parsed from the YAML section. This
was reserving the wrong register since it was setting the reserved
regs before parsing the correct one.

      

Some tests were relying on the default reserved set for the assumed
default calling convention.


https://reviews.llvm.org/D59853

Files:
  lib/CodeGen/MIRParser/MIRParser.cpp
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
  test/CodeGen/AMDGPU/endpgm-dce.mir
  test/CodeGen/AMDGPU/misched-killflags.mir
  test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
  test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir

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