[PATCH] D59758: [DAGCombiner] Combine OR as ADD when no common bits are set

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D59758#1441124 <https://reviews.llvm.org/D59758#1441124>, @bjope wrote:

> Hello reviewers! Do you think this is a good idea?


It's an interesting idea. :)

> I've mostly seen improvements for our OOT target when doing this, but for example llvm/test/CodeGen/X86/split-store.ll also exposes a case when we trigger a rewrite into using SUB.

Yes, we'd classify that as a slight regression for x86.

Do you have a sense of how many different folds we're missing in the tests where you show improvements? If it's a small number, we're probably better off just duplicating that code inside 'visitOR', so we don't have to deal with the regressions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59758/new/

https://reviews.llvm.org/D59758