[PATCH] D59758: [DAGCombiner] Combine OR as ADD when no common bits are set

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added a comment.

Hello reviewers! Do you think this is a good idea?

If you agree to the idea presented here, then I'll probably need some help from Hexagon regarding the llvm/test/CodeGen/Hexagon/subi-asl.ll test case (which no longer is triggering "subi-asl"). Should the test case be updated? Should we still get subi-asl here?

I've mostly seen improvements for our OOT target when doing this, but for example llvm/test/CodeGen/X86/split-store.ll also exposes a case when we trigger a rewrite into using SUB.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D59758/new/

https://reviews.llvm.org/D59758