[PATCH] D59295: [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.

[Neil Henning via Phabricator via llvm-commits]

sheredom marked 3 inline comments as done.
sheredom added inline comments.


================
Comment at: lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp:154
+    // physical registers.
+    const unsigned MovOp = TII->getMovOpcode(TRI->getPhysRegClass(PhysReg));
+
----------------
arsenm wrote:
> arsenm wrote:
> > Can't you just hardcoded this to v_mov_b32?
> I'm confused on the constraints for the WWM intrinsic, or lack thereof. The WWM instruction just uses "unknown" and the intrinsic allows any type. Can this be a 64-bit register or greater?
We only use WWM with 32-bit & 64-bit types in our stack - nothing else.


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Comment at: lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp:183-184
+
+      // And make it implicitly depend on exec (like all VALU movs should do).
+      MI.addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
+    }
----------------
arsenm wrote:
> I know we have a helper to do this somewhere
Couldn't find it myself in the code.


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  https://reviews.llvm.org/D59295/new/

https://reviews.llvm.org/D59295