[PATCH] D59295: [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp:154
+    // physical registers.
+    const unsigned MovOp = TII->getMovOpcode(TRI->getPhysRegClass(PhysReg));
+
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arsenm wrote:
> Can't you just hardcoded this to v_mov_b32?
I'm confused on the constraints for the WWM intrinsic, or lack thereof. The WWM instruction just uses "unknown" and the intrinsic allows any type. Can this be a 64-bit register or greater?


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  https://reviews.llvm.org/D59295/new/

https://reviews.llvm.org/D59295