[PATCH] D59558: [AArch64][GlobalISel] Add an optimization to select vector DUP instructions

[Jessica Paquette via Phabricator via llvm-commits]

paquette accepted this revision.
paquette added a comment.
This revision is now accepted and ready to land.

LGTM.

Some minor nits included.



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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:2354
+  //                                             %zerovec(<2 x s32>)
+  //
+  // We use the regbank of the scalar to determine which kind of dup to use.
----------------
Maybe include what we're transforming it into here?


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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:2387
+    return false;
+  for (unsigned i = 1; i < ZeroVec->getNumOperands() - 1; ++i) {
+    if (ZeroVec->getOperand(i).getReg() != ZeroVec->getOperand(1).getReg())
----------------
`for (unsigned i = 1, e = ZeroVec->getNumOperands() - 1; i < e; ++i)` ?


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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:2396
+  if (VecTy.getSizeInBits() != 128 || EltTy.getSizeInBits() < 32)
+    return false;
+  bool IsFP = ScalarRB->getID() == AArch64::FPRRegBankID;
----------------
Maybe some debug output here or a TODO or something?


================
Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:2420
+bool AArch64InstructionSelector::tryOptVectorShuffle(MachineInstr &I) const {
+  if (TM.getOptLevel() == CodeGenOpt::None)
+    return false;
----------------
This logic can probably be tightened a bit?


Repository:
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https://reviews.llvm.org/D59558