[PATCH] D59422: [SelectionDAG] Use SimplifyDemandedBits on truncated SCALAR_TO_VECTORs

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: test/CodeGen/AArch64/arm64-build-vector.ll:28
 ; CHECK-NEXT:    mov w8, #44672
-; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    dup.8h v1, w8
 ; CHECK-NEXT:    mul.8h v0, v0, v1
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This is in fact a regression, at least on some targets; on an A57, it has higher latency and uses an extra execution unit.

I'm guessing there's some issue with the priority between splat vs. zeroing in the case where the high elements are all undef?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59422/new/

https://reviews.llvm.org/D59422