[llvm] r356274 - [AArch64] Regenerate build vector tests

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Mar 15 10:17:37 2019
New Revision: 356274

URL: http://llvm.org/viewvc/llvm-project?rev=356274&view=rev
Log:
[AArch64] Regenerate build vector tests

Modified:
    llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll?rev=356274&r1=356273&r2=356274&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll Fri Mar 15 10:17:37 2019
@@ -1,14 +1,19 @@
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
 ; Check that building a vector from floats doesn't insert an unnecessary
 ; copy for lane zero.
 define <4 x float>  @foo(float %a, float %b, float %c, float %d) nounwind {
 ; CHECK-LABEL: foo:
-; CHECK-NOT: mov.s v0[0], v0[0]
-; CHECK: mov.s v0[1], v1[0]
-; CHECK: mov.s v0[2], v2[0]
-; CHECK: mov.s v0[3], v3[0]
-; CHECK: ret
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov.s v0[1], v1[0]
+; CHECK-NEXT:    mov.s v0[2], v2[0]
+; CHECK-NEXT:    mov.s v0[3], v3[0]
+; CHECK-NEXT:    ret
   %1 = insertelement <4 x float> undef, float %a, i32 0
   %2 = insertelement <4 x float> %1, float %b, i32 1
   %3 = insertelement <4 x float> %2, float %c, i32 2
@@ -18,9 +23,11 @@ define <4 x float>  @foo(float %a, float
 
 define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
 ; CHECK-LABEL: build_all_zero:
-; CHECK: mov	w[[GREG:[0-9]+]], #44672
-; CHECK-NEXT:	fmov	s[[FREG:[0-9]+]], w[[GREG]]
-; CHECK-NEXT:	mul.8h	v0, v0, v[[FREG]]
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #44672
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    mul.8h v0, v0, v1
+; CHECK-NEXT:    ret
   %b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
   %c = mul <8 x i16> %b, <i16 -20864, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
   ret <8 x i16> %c
@@ -33,7 +40,9 @@ define <8 x i16> @build_all_zero(<8 x i1
 ; assertion failure.
 define <8 x i16> @concat_2_build_vector(<4 x i16> %in0) {
 ; CHECK-LABEL: concat_2_build_vector:
-; CHECK: movi
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi.2d v0, #0000000000000000
+; CHECK-NEXT:    ret
   %vshl_n = shl <4 x i16> %in0, <i16 8, i16 8, i16 8, i16 8>
   %vshl_n2 = shl <4 x i16> %vshl_n, <i16 9, i16 9, i16 9, i16 9>
   %shuffle.i = shufflevector <4 x i16> %vshl_n2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -46,9 +55,11 @@ define <8 x i16> @concat_2_build_vector(
 ; constant prevents earlier passes from replacing the BUILD_VECTOR.
 define void @widen_f16_build_vector(half* %addr) {
 ; CHECK-LABEL: widen_f16_build_vector:
-; CHECK: mov    w[[GREG:[0-9]+]], #13294
-; CHECK: dup.4h v0, w[[GREG]]
-; CHECK: str    s0, [x0]
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #13294
+; CHECK-NEXT:    dup.4h v0, w8
+; CHECK-NEXT:    str s0, [x0]
+; CHECK-NEXT:    ret
   %1 = bitcast half* %addr to <2 x half>*
   store <2 x half> <half 0xH33EE, half 0xH33EE>, <2 x half>* %1, align 2
   ret void
@@ -56,21 +67,23 @@ define void @widen_f16_build_vector(half
 
 ; Check that a single element vector is constructed with a mov
 define <1 x i64> @single_element_vector_i64(<1 x i64> %arg) {
-; CHECK-LABEL: single_element_vector_i64
-; CHECK: orr w[[GREG:[0-9]+]], wzr, #0x1
-; CHECK: fmov d[[DREG:[0-9]+]], x[[GREG]]
-; CHECK: add d0, d0, d[[DREG]]
-; CHECK: ret
+; CHECK-LABEL: single_element_vector_i64:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    orr w8, wzr, #0x1
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    add d0, d0, d1
+; CHECK-NEXT:    ret
 entry:
   %add = add <1 x i64> %arg, <i64 1>
   ret <1 x i64> %add
 }
 
 define <1 x double> @single_element_vector_double(<1 x double> %arg) {
-; CHECK-LABEL: single_element_vector_double
-; CHECK: fmov d[[DREG:[0-9]+]], #1.00000000
-; CHECK: fadd d0, d0, d[[DREG]]
-; CHECK: ret
+; CHECK-LABEL: single_element_vector_double:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fmov d1, #1.00000000
+; CHECK-NEXT:    fadd d0, d0, d1
+; CHECK-NEXT:    ret
 entry:
   %add = fadd <1 x double> %arg, <double 1.0>
   ret <1 x double> %add