[llvm] r355983 - [Test] Add tests for implicit null checks on atomic/volatile instructions
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 12 14:09:58 PDT 2019
Author: reames
Date: Tue Mar 12 14:09:58 2019
New Revision: 355983
URL: http://llvm.org/viewvc/llvm-project?rev=355983&view=rev
Log:
[Test] Add tests for implicit null checks on atomic/volatile instructions
Modified:
llvm/trunk/test/CodeGen/X86/implicit-null-check.ll
Modified: llvm/trunk/test/CodeGen/X86/implicit-null-check.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-check.ll?rev=355983&r1=355982&r2=355983&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/implicit-null-check.ll (original)
+++ llvm/trunk/test/CodeGen/X86/implicit-null-check.ll Tue Mar 12 14:09:58 2019
@@ -24,14 +24,91 @@ define i32 @imp_null_check_load(i32* %x)
ret i32 %t
}
+; TODO: can make implicit
+define i32 @imp_null_check_unordered_load(i32* %x) {
+; CHECK-LABEL: imp_null_check_unordered_load:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: je LBB1_1
+; CHECK-NEXT: ## %bb.2: ## %not_null
+; CHECK-NEXT: movl (%rdi), %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB1_1: ## %is_null
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: retq
+
+ entry:
+ %c = icmp eq i32* %x, null
+ br i1 %c, label %is_null, label %not_null, !make.implicit !0
+
+ is_null:
+ ret i32 42
+
+ not_null:
+ %t = load atomic i32, i32* %x unordered, align 4
+ ret i32 %t
+}
+
+;; Probably could be implicit, but we're conservative for now
+define i32 @imp_null_check_seq_cst_load(i32* %x) {
+; CHECK-LABEL: imp_null_check_seq_cst_load:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: je LBB2_1
+; CHECK-NEXT: ## %bb.2: ## %not_null
+; CHECK-NEXT: movl (%rdi), %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB2_1: ## %is_null
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: retq
+
+ entry:
+ %c = icmp eq i32* %x, null
+ br i1 %c, label %is_null, label %not_null, !make.implicit !0
+
+ is_null:
+ ret i32 42
+
+ not_null:
+ %t = load atomic i32, i32* %x seq_cst, align 4
+ ret i32 %t
+}
+
+;; Might be memory mapped IO, so can't rely on fault behavior
+define i32 @imp_null_check_volatile_load(i32* %x) {
+; CHECK-LABEL: imp_null_check_volatile_load:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: je LBB3_1
+; CHECK-NEXT: ## %bb.2: ## %not_null
+; CHECK-NEXT: movl (%rdi), %eax
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB3_1: ## %is_null
+; CHECK-NEXT: movl $42, %eax
+; CHECK-NEXT: retq
+
+ entry:
+ %c = icmp eq i32* %x, null
+ br i1 %c, label %is_null, label %not_null, !make.implicit !0
+
+ is_null:
+ ret i32 42
+
+ not_null:
+ %t = load volatile i32, i32* %x, align 4
+ ret i32 %t
+}
+
+
+
define i32 @imp_null_check_gep_load(i32* %x) {
; CHECK-LABEL: imp_null_check_gep_load:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: Ltmp1:
-; CHECK-NEXT: movl 128(%rdi), %eax ## on-fault: LBB1_1
+; CHECK-NEXT: movl 128(%rdi), %eax ## on-fault: LBB4_1
; CHECK-NEXT: ## %bb.2: ## %not_null
; CHECK-NEXT: retq
-; CHECK-NEXT: LBB1_1: ## %is_null
+; CHECK-NEXT: LBB4_1: ## %is_null
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retq
@@ -52,11 +129,11 @@ define i32 @imp_null_check_add_result(i3
; CHECK-LABEL: imp_null_check_add_result:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: Ltmp2:
-; CHECK-NEXT: addl (%rdi), %esi ## on-fault: LBB2_1
+; CHECK-NEXT: addl (%rdi), %esi ## on-fault: LBB5_1
; CHECK-NEXT: ## %bb.2: ## %not_null
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: retq
-; CHECK-NEXT: LBB2_1: ## %is_null
+; CHECK-NEXT: LBB5_1: ## %is_null
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retq
@@ -77,12 +154,12 @@ define i32 @imp_null_check_hoist_over_un
; CHECK-LABEL: imp_null_check_hoist_over_unrelated_load:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: Ltmp3:
-; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB3_1
+; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB6_1
; CHECK-NEXT: ## %bb.2: ## %not_null
; CHECK-NEXT: movl (%rsi), %ecx
; CHECK-NEXT: movl %ecx, (%rdx)
; CHECK-NEXT: retq
-; CHECK-NEXT: LBB3_1: ## %is_null
+; CHECK-NEXT: LBB6_1: ## %is_null
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retq
@@ -104,16 +181,16 @@ define i32 @imp_null_check_via_mem_compa
; CHECK-LABEL: imp_null_check_via_mem_comparision:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: Ltmp4:
-; CHECK-NEXT: cmpl %esi, 4(%rdi) ## on-fault: LBB4_3
+; CHECK-NEXT: cmpl %esi, 4(%rdi) ## on-fault: LBB7_3
; CHECK-NEXT: ## %bb.1: ## %not_null
-; CHECK-NEXT: jge LBB4_2
+; CHECK-NEXT: jge LBB7_2
; CHECK-NEXT: ## %bb.4: ## %ret_100
; CHECK-NEXT: movl $100, %eax
; CHECK-NEXT: retq
-; CHECK-NEXT: LBB4_3: ## %is_null
+; CHECK-NEXT: LBB7_3: ## %is_null
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retq
-; CHECK-NEXT: LBB4_2: ## %ret_200
+; CHECK-NEXT: LBB7_2: ## %ret_200
; CHECK-NEXT: movl $200, %eax
; CHECK-NEXT: retq
@@ -142,12 +219,12 @@ define i32 @imp_null_check_gep_load_with
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: ## kill: def $esi killed $esi def $rsi
; CHECK-NEXT: Ltmp5:
-; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB5_1
+; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB8_1
; CHECK-NEXT: ## %bb.2: ## %not_null
; CHECK-NEXT: addl %edi, %esi
; CHECK-NEXT: leal 4(%rax,%rsi), %eax
; CHECK-NEXT: retq
-; CHECK-NEXT: LBB5_1: ## %is_null
+; CHECK-NEXT: LBB8_1: ## %is_null
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retq
@@ -171,10 +248,10 @@ define void @imp_null_check_store(i32* %
; CHECK-LABEL: imp_null_check_store:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: Ltmp6:
-; CHECK-NEXT: movl $1, (%rdi) ## on-fault: LBB6_1
+; CHECK-NEXT: movl $1, (%rdi) ## on-fault: LBB9_1
; CHECK-NEXT: ## %bb.2: ## %not_null
; CHECK-NEXT: retq
-; CHECK-NEXT: LBB6_1: ## %is_null
+; CHECK-NEXT: LBB9_1: ## %is_null
; CHECK-NEXT: retq
entry:
@@ -189,14 +266,38 @@ define void @imp_null_check_store(i32* %
ret void
}
+;; TODO: can be implicit
+define void @imp_null_check_unordered_store(i32* %x) {
+; CHECK-LABEL: imp_null_check_unordered_store:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: je LBB10_1
+; CHECK-NEXT: ## %bb.2: ## %not_null
+; CHECK-NEXT: movl $1, (%rdi)
+; CHECK-NEXT: retq
+; CHECK-NEXT: LBB10_1: ## %is_null
+; CHECK-NEXT: retq
+
+ entry:
+ %c = icmp eq i32* %x, null
+ br i1 %c, label %is_null, label %not_null, !make.implicit !0
+
+ is_null:
+ ret void
+
+ not_null:
+ store atomic i32 1, i32* %x unordered, align 4
+ ret void
+}
+
define i32 @imp_null_check_neg_gep_load(i32* %x) {
; CHECK-LABEL: imp_null_check_neg_gep_load:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: Ltmp7:
-; CHECK-NEXT: movl -128(%rdi), %eax ## on-fault: LBB7_1
+; CHECK-NEXT: movl -128(%rdi), %eax ## on-fault: LBB11_1
; CHECK-NEXT: ## %bb.2: ## %not_null
; CHECK-NEXT: retq
-; CHECK-NEXT: LBB7_1: ## %is_null
+; CHECK-NEXT: LBB11_1: ## %is_null
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retq
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