[PATCH] D58015: [SelectionDAG][AArch64] Legalize VECREDUCE

[Nikita Popov via Phabricator via llvm-commits]

nikic added a comment.

I've extended the expansion code to use a tree reduction for pow2 vectors as long as we have the necessary operations. I think the most relevant example is the `v16f32` reduction for `fadd`:

  define float @test_v16f32(<16 x float> %a) nounwind {
  ; CHECK-LABEL: test_v16f32:
  ; CHECK:       // %bb.0:
  ; CHECK-NEXT:    fadd v1.4s, v1.4s, v3.4s
  ; CHECK-NEXT:    fadd v0.4s, v0.4s, v2.4s
  ; CHECK-NEXT:    fadd v0.4s, v0.4s, v1.4s
  ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
  ; CHECK-NEXT:    fadd v0.2s, v0.2s, v1.2s
  ; CHECK-NEXT:    faddp s0, v0.2s
  ; CHECK-NEXT:    ret
    %b = call fast nnan float @llvm.experimental.vector.reduce.fadd.f32.v16f32(float 0.0, <16 x float> %a)
    ret float %b
  }

Not being overly familiar with AArch64 this looks optimal. Results for "weird" vector sizes are sometimes quite bad though (on the other hand, the current pre-sdag expansion code doesn't support them at all).


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