[PATCH] D58903: [AMDGPU] Added v5i32 and v5f32 register classes

[Tim Renouf via Phabricator via llvm-commits]

tpr updated this revision to Diff 189575.
tpr added a comment.
Herald added a subscriber: qcolombet.

V2: Fixed missing part of change, including defaulting v5 operations to
expand. Fixed broken v5f32 select. Fixed reg class priorities.
Fixed spilling and asm constraints, and added sgpr spill test.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58903/new/

https://reviews.llvm.org/D58903

Files:
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.td
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  test/CodeGen/AMDGPU/select-vectors.ll
  test/CodeGen/AMDGPU/spill-wide-sgpr.ll

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