[PATCH] D59021: [ARM] [FIX] Restrict vfmal.f16 and vfmsl.f16 indexed operand to d[0-7]

[Diogo N. Sampaio via Phabricator via llvm-commits]

dnsampaio created this revision.
dnsampaio added reviewers: olista01, SjoerdMeijer, t.p.northover.
Herald added subscribers: llvm-commits, arphaman, kristof.beyls, javed.absar.
Herald added a project: LLVM.

The q indexed variant of vfmal.f16 and vfmsl.f16 allows only d0 to d7 in the indexed operand.
Currently all registers are accepted, but the 2 upper bits are ignored:

  vfmsl.f16       q0, d1, d0[0]     @ encoding: [0x50,0x08,0x11,0xfe]
  vfmsl.f16       q0, d1, d8[0]     @ encoding: [0x50,0x08,0x11,0xfe]
  vfmsl.f16       q0, d1, d16[0]   @ encoding: [0x50,0x08,0x11,0xfe]

This patch restrict the indexed operand to be between d0 and d7.


Repository:
  rL LLVM

https://reviews.llvm.org/D59021

Files:
  lib/Target/ARM/ARMInstrNEON.td
  test/MC/ARM/armv8a-fpmul-error.s


Index: test/MC/ARM/armv8a-fpmul-error.s
===================================================================
--- test/MC/ARM/armv8a-fpmul-error.s
+++ test/MC/ARM/armv8a-fpmul-error.s
@@ -6,6 +6,8 @@
 vfmal.f16 q0, d1, d2[4]
 VFMSL.F16 Q0, D1, D2[4]
 vfmal.f16 q0, d1, d2[-1]
+VFMSL.F16 Q0, D1, D8[0]
+vfmal.f16 q0, d1, d8[0]
 
 //CHECK-ERROR:      error: invalid operand for instruction
 //CHECK-ERROR-NEXT: VFMAL.F16 D0, S1, S2[2]
@@ -25,3 +27,21 @@
 //CHECK-ERROR-NEXT: error: invalid operand for instruction
 //CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[-1]
 //CHECK-ERROR-NEXT:                     ^
+//CHECK-ERROR-NEXT: : error: invalid instruction, any one of the following would fix this:
+//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0]
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: : note: operand must be a register in range [d0, d7]
+//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0]
+//CHECK-ERROR-NEXT:                   ^
+//CHECK-ERROR-NEXT: : note: too many operands for instruction
+//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D8[0]
+//CHECK-ERROR-NEXT:                     ^
+//CHECK-ERROR-NEXT: : error: invalid instruction, any one of the following would fix this:
+//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0]
+//CHECK-ERROR-NEXT: ^
+//CHECK-ERROR-NEXT: : note: operand must be a register in range [d0, d7]
+//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0]
+//CHECK-ERROR-NEXT:                   ^
+//CHECK-ERROR-NEXT: 1: note: too many operands for instruction
+//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d8[0]
+//CHECK-ERROR-NEXT:                     ^
Index: lib/Target/ARM/ARMInstrNEON.td
===================================================================
--- lib/Target/ARM/ARMInstrNEON.td
+++ lib/Target/ARM/ARMInstrNEON.td
@@ -438,6 +438,19 @@
   let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
 }
 
+// Vq, Vd, Vd[0-7], Idx[0-3]
+class Vec_Q_D_D8_Idx2_Base<string opc, string type, bits<2> op21_20,
+  bit op23, bit op6, bit op4>
+  : N3VLaneCP8<op23, op21_20, op6, op4, (outs QPR:$Vd),
+               (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$idx),
+               IIC_VMACD, opc, type, "$Vd, $Vn, $Vm$idx", "", []> {
+  bits<2> idx;
+  let Inst{5} = idx{1};
+  let Inst{3} = idx{0};
+
+  let Predicates = [HasNEON];
+}
+
 def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
   return cast<LoadSDNode>(N)->getAlignment() >= 8;
 }]>;
@@ -5150,8 +5163,8 @@
 def VFMSLQ  : N3VCP8F16Q1<"vfmsl", QPR, DPR, DPR, 0b01, 0b10, 1>;
 def VFMALDI : VFMQ0<"vfmal", 0b00>;
 def VFMSLDI : VFMQ0<"vfmsl", 0b01>;
-def VFMALQI : VFMQ1<"vfmal", 0b00>;
-def VFMSLQI : VFMQ1<"vfmsl", 0b01>;
+def VFMALQI : Vec_Q_D_D8_Idx2_Base<"vfmal", "f16", 0b00, 0, 1, 1>;
+def VFMSLQI : Vec_Q_D_D8_Idx2_Base<"vfmsl", "f16", 0b01, 0, 1, 1>;
 }
 } // HasNEON, HasFP16FML
 


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