[PATCH] D58980: [ARC] Add more load/store variants and simple pass to generate postincrement instructions

[Denis Antrushin via Phabricator via llvm-commits]

dantrushin created this revision.
dantrushin added reviewers: petecoup, kparzysz.
Herald added subscribers: hiraditya, mgorny.
Herald added a project: LLVM.

On ARC ISA, general format of load instruction is this:

      LD<zz><.x><.aa><.di> a, [b,c]
  And general format of store is this:
      ST<zz><.aa><.di> c, [b,s9]


Where:

    
  <zz> is data size field and can be one of
    <empty> (bits 00) - Word (32-bit), default behavior
    B             (bits 01) - Byte
    H             (bits 10) - Half-word (16-bit)
    
   <.x> is data extend mode:
    <empty> (bit 0) - If size is not Word(32-bit), then data is zero extended
    X             (bit 1) - If size is not Word(32-bit), then data is sign extended
    
   <.aa> is address write-back mode:
    <empty> (bits 00) - no write-back
    .AW     (bits 01) - Preincrement, base register is updated pre memory transaction
    .AB      (bits 10) - Postincrement, base register is updated post memory transaction
    
   <.di> is cache bypass mode:
    <empty> (bit 0) - Cached memory access, default mode
    .DI           (bit 1) - Non-cached data memory access
    
    This patch adds these load/store instruction variants to the ARC backend and also
    adds simple pass to generate postincrement load/store instructions


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D58980

Files:
  llvm/lib/Target/ARC/ARC.h
  llvm/lib/Target/ARC/ARCFrameLowering.cpp
  llvm/lib/Target/ARC/ARCInstrFormats.td
  llvm/lib/Target/ARC/ARCInstrInfo.cpp
  llvm/lib/Target/ARC/ARCInstrInfo.h
  llvm/lib/Target/ARC/ARCInstrInfo.td
  llvm/lib/Target/ARC/ARCOptAddrMode.cpp
  llvm/lib/Target/ARC/ARCTargetMachine.cpp
  llvm/lib/Target/ARC/CMakeLists.txt
  llvm/test/CodeGen/ARC/addrmode.ll

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