[PATCH] D58904: [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
Herald added subscribers: llvm-commits, t-tye, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, arsenm.
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On gfx6, a dwordx3 buffer load intrinsic is implemented as a dwordx4
instruction, and a dwordx3 buffer store intrinsic is not supported.
We need to support the dwordx3 load intrinsic because it is generated by
subtarget-unaware code in InstCombine.

Change-Id: I016729d8557b98a52f529638ae97c340a5922a4e


Repository:
  rL LLVM

https://reviews.llvm.org/D58904

Files:
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.h
  lib/Target/AMDGPU/BUFInstructions.td
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.h
  lib/Target/AMDGPU/SIInstrInfo.td
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll

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