[PATCH] D52138: [Thumb] Add some integer abs testcases for different typesizes.

[Ivan Kulagin via Phabricator via llvm-commits]

ikulagin updated this revision to Diff 188785.
ikulagin added a comment.

Update by `update_llc_test_checks.py`.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D52138/new/

https://reviews.llvm.org/D52138

Files:
  test/CodeGen/Thumb/iabs.ll


Index: test/CodeGen/Thumb/iabs.ll
===================================================================
--- test/CodeGen/Thumb/iabs.ll
+++ test/CodeGen/Thumb/iabs.ll
@@ -1,20 +1,58 @@
-; RUN: llc < %s -mtriple=thumb-unknown-unknown -filetype=obj -o %t.o
-; RUN: llvm-objdump -disassemble -arch-name=thumb %t.o | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s
 
-define i32 @test(i32 %a) {
-        %tmp1neg = sub i32 0, %a
-        %b = icmp sgt i32 %a, -1
-        %abs = select i1 %b, i32 %a, i32 %tmp1neg
-        ret i32 %abs
-
-; This test just checks that 4 instructions were emitted
+define i8 @test_i8(i8 %a) nounwind {
+; CHECK-LABEL: test_i8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    sxtb r1, r0
+; CHECK-NEXT:    asrs r1, r1, #7
+; CHECK-NEXT:    adds r0, r0, r1
+; CHECK-NEXT:    eors r0, r1
+; CHECK-NEXT:    bx lr
+  %tmp1neg = sub i8 0, %a
+  %b = icmp sgt i8 %a, -1
+  %abs = select i1 %b, i8 %a, i8 %tmp1neg
+  ret i8 %abs
+}
 
-; CHECK:      {{text}}
-; CHECK:      0:
-; CHECK-NEXT: 2:
-; CHECK-NEXT: 4:
-; CHECK-NEXT: 6:
+define i16 @test_i16(i16 %a) nounwind {
+; CHECK-LABEL: test_i16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    sxth r1, r0
+; CHECK-NEXT:    asrs r1, r1, #15
+; CHECK-NEXT:    adds r0, r0, r1
+; CHECK-NEXT:    eors r0, r1
+; CHECK-NEXT:    bx lr
+  %tmp1neg = sub i16 0, %a
+  %b = icmp sgt i16 %a, -1
+  %abs = select i1 %b, i16 %a, i16 %tmp1neg
+  ret i16 %abs
+}
 
-; CHECK-NOT: 8:
+define i32 @test_i32(i32 %a) nounwind {
+; CHECK-LABEL: test_i32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    asrs r1, r0, #31
+; CHECK-NEXT:    adds r0, r0, r1
+; CHECK-NEXT:    eors r0, r1
+; CHECK-NEXT:    bx lr
+  %tmp1neg = sub i32 0, %a
+  %b = icmp sgt i32 %a, -1
+  %abs = select i1 %b, i32 %a, i32 %tmp1neg
+  ret i32 %abs
 }
 
+define i64 @test_i64(i64 %a) nounwind {
+; CHECK-LABEL: test_i64:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    asrs r2, r1, #31
+; CHECK-NEXT:    adds r0, r0, r2
+; CHECK-NEXT:    adcs r1, r2
+; CHECK-NEXT:    eors r0, r2
+; CHECK-NEXT:    eors r1, r2
+; CHECK-NEXT:    bx lr
+  %tmp1neg = sub i64 0, %a
+  %b = icmp sgt i64 %a, -1
+  %abs = select i1 %b, i64 %a, i64 %tmp1neg
+  ret i64 %abs
+}


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