[PATCH] D58684: [AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:1979
+      SubregIdx = AArch64::ssub;
+    } else {
+      Opc = AArch64::INSvi64gpr;
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Is it possible that `EltSize` could be something invalid when it's coming into here? Should we have some error-handling?


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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:1981
+      Opc = AArch64::INSvi64gpr;
+      SubregIdx = AArch64::dsub;
+    }
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Not important for this patch, but I've noticed that we have a lot of this subregister calculation code floating around.

Might be good to migrate some of this over to using a utility function for calculating the subregister index. `getSubRegForClass` does it, but I don't know if that's the best choice.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58684/new/

https://reviews.llvm.org/D58684