[llvm] r354900 - [MIPS GlobalISel] Select G_UADDO

[Petar Avramovic via llvm-commits]

Author: petar.avramovic
Date: Tue Feb 26 09:22:42 2019
New Revision: 354900

URL: http://llvm.org/viewvc/llvm-project?rev=354900&view=rev
Log:
[MIPS GlobalISel] Select G_UADDO

Lower G_UADDO.
Legalize G_UADDO for MIPS32

Differential Revision: https://reviews.llvm.org/D58671

Modified:
    llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
    llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
    llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll

Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=354900&r1=354899&r2=354900&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Tue Feb 26 09:22:42 2019
@@ -1545,6 +1545,18 @@ LegalizerHelper::lower(MachineInstr &MI,
   case TargetOpcode::G_CTTZ:
   case TargetOpcode::G_CTPOP:
     return lowerBitCount(MI, TypeIdx, Ty);
+  case G_UADDO: {
+    unsigned Res = MI.getOperand(0).getReg();
+    unsigned CarryOut = MI.getOperand(1).getReg();
+    unsigned LHS = MI.getOperand(2).getReg();
+    unsigned RHS = MI.getOperand(3).getReg();
+
+    MIRBuilder.buildAdd(Res, LHS, RHS);
+    MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
+
+    MI.eraseFromParent();
+    return Legalized;
+  }
   case G_UADDE: {
     unsigned Res = MI.getOperand(0).getReg();
     unsigned CarryOut = MI.getOperand(1).getReg();

Modified: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp?rev=354900&r1=354899&r2=354900&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp Tue Feb 26 09:22:42 2019
@@ -32,7 +32,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(con
       .legalFor({s32})
       .minScalar(0, s32);
 
-  getActionDefinitionsBuilder({G_UADDE, G_USUBO, G_USUBE})
+  getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE})
       .lowerFor({{s32, s1}});
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})

Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir?rev=354900&r1=354899&r2=354900&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/add.mir Tue Feb 26 09:22:42 2019
@@ -11,6 +11,7 @@
   define void @add_i16_aext() {entry: ret void}
   define void @add_i64() {entry: ret void}
   define void @add_i128() {entry: ret void}
+  define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag) { ret void }
 
 ...
 ---
@@ -334,3 +335,35 @@ body:             |
     RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
 
 ...
+---
+name:            uadd_with_overflow
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: uadd_with_overflow
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
+    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+    ; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag)
+    ; MIPS32: G_STORE [[ADD]](s32), [[COPY2]](p0) :: (store 4 into %ir.padd)
+    ; MIPS32: RetRA
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(p0) = COPY $a2
+    %3:_(p0) = COPY $a3
+    %4:_(s32), %5:_(s1) = G_UADDO %0, %1
+    G_STORE %5(s1), %3(p0) :: (store 1 into %ir.pcarry_flag)
+    G_STORE %4(s32), %2(p0) :: (store 4 into %ir.padd)
+    RetRA
+
+...

Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll?rev=354900&r1=354899&r2=354900&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll Tue Feb 26 09:22:42 2019
@@ -160,3 +160,24 @@ entry:
   %add = add i128 %b, %a
   ret i128 %add
 }
+
+declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
+define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag) {
+; MIPS32-LABEL: uadd_with_overflow:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    addu $4, $4, $5
+; MIPS32-NEXT:    sltu $5, $4, $5
+; MIPS32-NEXT:    lui $1, 0
+; MIPS32-NEXT:    ori $1, $1, 1
+; MIPS32-NEXT:    and $1, $5, $1
+; MIPS32-NEXT:    sb $1, 0($7)
+; MIPS32-NEXT:    sw $4, 0($6)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+  %res = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lhs, i32 %rhs)
+  %carry_flag = extractvalue { i32, i1 } %res, 1
+  %add = extractvalue { i32, i1 } %res, 0
+  store i1 %carry_flag, i1* %pcarry_flag
+  store i32 %add, i32* %padd
+  ret void
+}