[PATCH] D58512: AMDGPU/GlobalISel: Insert waterfall loop for vector indexing

[Matt Arsenault via Phabricator via llvm-commits]

arsenm marked 2 inline comments as done.
arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:333-336
+/// Legalize instruction \p MI where operands in \p OpIndices must be SGPRs.  If
+/// any of the required SGPR operands are VGPRs, perform a waterfall loop to
+/// execute the instruction for each unique combination of values in all lanes
+/// in the wave. The block will be split such that new blocks
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scott.linder wrote:
> Could you indicate the current limitations? I.e. only one, 32-bit operand per machine instruction.
There's not much point since I have patches queued up to implement most of the rest of these restrictions


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Comment at: lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:385
+
+  // Don't bother using generic instructions/registers for the exec mask.
+  B.buildInstr(TargetOpcode::IMPLICIT_DEF)
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scott.linder wrote:
> Is this because we wouldn't gain anything more in regbankselect/instructionselect? Or because we don't need the type checking in G_PHI when we control the types? Or something else? I'm just curious as I'm not very familiar with GISel.
We can't really do anything with it, so might as well select it to the final instruction. The same kind of applies to the other phis, so I might revisit those later.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58512/new/

https://reviews.llvm.org/D58512