[PATCH] D58512: AMDGPU/GlobalISel: Insert waterfall loop for vector indexing

[Scott Linder via Phabricator via llvm-commits]

scott.linder added inline comments.


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Comment at: lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:333-336
+/// Legalize instruction \p MI where operands in \p OpIndices must be SGPRs.  If
+/// any of the required SGPR operands are VGPRs, perform a waterfall loop to
+/// execute the instruction for each unique combination of values in all lanes
+/// in the wave. The block will be split such that new blocks
----------------
Could you indicate the current limitations? I.e. only one, 32-bit operand per machine instruction.


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Comment at: lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:385
+
+  // Don't bother using generic instructions/registers for the exec mask.
+  B.buildInstr(TargetOpcode::IMPLICIT_DEF)
----------------
Is this because we wouldn't gain anything more in regbankselect/instructionselect? Or because we don't need the type checking in G_PHI when we control the types? Or something else? I'm just curious as I'm not very familiar with GISel.


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Comment at: lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp:460
+
+      // FIXME: Need to and each conditon
+
----------------
condition


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58512/new/

https://reviews.llvm.org/D58512