[PATCH] D58481: [AMDGPU] fix commuted case of sub combine

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 187707.
rampitec added a comment.
This revision is now accepted and ready to land.

Disabled commuted case completely.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58481/new/

https://reviews.llvm.org/D58481

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/combine-cond-add-sub.ll


Index: test/CodeGen/AMDGPU/combine-cond-add-sub.ll
===================================================================
--- test/CodeGen/AMDGPU/combine-cond-add-sub.ll
+++ test/CodeGen/AMDGPU/combine-cond-add-sub.ll
@@ -127,6 +127,25 @@
   ret void
 }
 
+; GCN-LABEL: {{^}}sub_sube_commuted:
+; GCN:     v_subb
+; GCN:     v_sub_
+; GCN:     v_add_
+define amdgpu_kernel void @sub_sube_commuted(i32 addrspace(1)* nocapture %arg, i32 %a) {
+bb:
+  %x = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %y = tail call i32 @llvm.amdgcn.workitem.id.y()
+  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
+  %v = load i32, i32 addrspace(1)* %gep, align 4
+  %cmp = icmp ugt i32 %x, %y
+  %ext = sext i1 %cmp to i32
+  %adde = add i32 %v, %ext
+  %sub = sub i32 %adde, %a
+  %sub2 = sub i32 100, %sub
+  store i32 %sub2, i32 addrspace(1)* %gep, align 4
+  ret void
+}
+
 ; GCN-LABEL: {{^}}sube_sub:
 ; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
 ; GCN: v_subb_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC]]
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -8616,14 +8616,10 @@
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
 
-  unsigned Opc = LHS.getOpcode();
-  if (Opc != ISD::SUBCARRY)
-    std::swap(RHS, LHS);
-
   if (LHS.getOpcode() == ISD::SUBCARRY) {
     // sub (subcarry x, 0, cc), y => subcarry x, y, cc
     auto C = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
-    if (!C || C->getZExtValue() != 0)
+    if (!C || !C->isNullValue())
       return SDValue();
     SDValue Args[] = { LHS.getOperand(0), RHS, LHS.getOperand(2) };
     return DAG.getNode(ISD::SUBCARRY, SDLoc(N), LHS->getVTList(), Args);


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