[llvm] r354473 - [Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTEND

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Feb 20 07:05:19 2019
New Revision: 354473

URL: http://llvm.org/viewvc/llvm-project?rev=354473&view=rev
Log:
[Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTEND

Added:
    llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=354473&r1=354472&r2=354473&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Wed Feb 20 07:05:19 2019
@@ -848,6 +848,9 @@ void HexagonDAGToDAGISel::SelectD2P(SDNo
 void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) {
   const SDLoc &dl(N);
   MVT ResTy = N->getValueType(0).getSimpleVT();
+  // The argument to V2Q should be a single vector.
+  MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy;
+  assert(HST->getVectorLength() * 8 == OpTy.getSizeInBits());
 
   SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
   SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);
@@ -859,6 +862,8 @@ void HexagonDAGToDAGISel::SelectV2Q(SDNo
 void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) {
   const SDLoc &dl(N);
   MVT ResTy = N->getValueType(0).getSimpleVT();
+  // The result of V2Q should be a single vector.
+  assert(HST->getVectorLength() * 8 == ResTy.getSizeInBits());
 
   SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32);
   SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C);

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp?rev=354473&r1=354472&r2=354473&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp Wed Feb 20 07:05:19 2019
@@ -1541,6 +1541,8 @@ HexagonTargetLowering::LowerHvxOperation
       case ISD::SRL:
       case ISD::SETCC:
       case ISD::VSELECT:
+      case ISD::SIGN_EXTEND:
+      case ISD::ZERO_EXTEND:
       case ISD::SIGN_EXTEND_INREG:
         return SplitHvxPairOp(Op, DAG);
     }

Added: llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll?rev=354473&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll Wed Feb 20 07:05:19 2019
@@ -0,0 +1,16 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Make sure that this doesn't crash.
+; CHECK: vadd
+
+define void @foo(<64 x i32>* %a0, <64 x i32>* %a1) #0 {
+  %v0 = load <64 x i32>, <64 x i32>* %a0, align 128
+  %v1 = load <64 x i32>, <64 x i32>* %a1, align 128
+  %v2 = icmp sgt <64 x i32> %v0, zeroinitializer
+  %v3 = sext <64 x i1> %v2 to <64 x i32>
+  %v4 = add nsw <64 x i32> %v1, %v3
+  store <64 x i32> %v4, <64 x i32>* %a1, align 128
+  ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length128b" }