[PATCH] D58348: [AArch64] Fix for bug 35094 atomicrmw on Armv8.1-A+lse

Christof Douma via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 21 03:38:57 PST 2019


christof marked an inline comment as done.
christof added a comment.

In D58348#1404995 <https://reviews.llvm.org/D58348#1404995>, @efriedma wrote:

> Are you sure that Bugzilla link is right?


Fixed. The bug number in the subject was the correct one.

> I agree this is a problem according to the formal model, although it would be kind of weird to run into it (you can't tell whether the happens-before edge formed without reading the value at some point, so the code would have to load the result of the atomic operation at some point).

It might be an edge case, I'm not sure, to be honest. I'll go see if I can get some better idea of that. I though that it would be good to adhere to the formal model to prevent surprise, so if there is an example that breaks, we ought to prevent that. Is that up for debate in case this is an edge case that is unlikely to be hit?



================
Comment at: lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp:71
 
+// Instructions that load their 'read' operation for a subesquent fence acquire
+// (DMB LD) once the zero register is used.
----------------
s/load/lose/


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https://reviews.llvm.org/D58348





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