[PATCH] D56005: [RFC] [LLVM] Allocatable Global Register Variables for ARM

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Sorry about the delay.

It looks like there's a conflict between reserving r7/r11 and the use of r7/r11 as a frame pointer.  (See useR7AsFramePointer.)  Similarly, there's a conflict between reserving r6 and its use as a base pointer.  It's okay if some combinations print an error, but we shouldn't silently miscompile.



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Comment at: lib/Target/ARM/ARMSubtarget.h:722
+    if (i == 9 && isTargetMachO() && !HasV6Ops) {
+      return true;
+    }
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Can we handle this in initSubtargetFeatures instead, like we do for rwpi?  It's sort of confusing to follow.


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Comment at: test/CodeGen/ARM/reg-alloc-no-alignment.ll:16
+declare dso_local i32 @bar(...) #1
\ No newline at end of file

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Newline.


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  https://reviews.llvm.org/D56005/new/

https://reviews.llvm.org/D56005