[PATCH] D58402: RegBankSelect: Allow targets to introduce control flow for mapping

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: qcolombet.
Herald added subscribers: tpr, wdng.

For AMDGPU, if an operand requires an SGPR but is only available as a
VGPR, a loop needs to be introduced until to execute the instruction
with each unique combination of values across all lanes. The rest of
the instructions in the block will be moved to a new block following
the loop. Check if the next instruction's parent changed, and update
the iterators and insertion block if this happened.

Tests will be included in a future patch.


https://reviews.llvm.org/D58402

Files:
  lib/CodeGen/GlobalISel/RegBankSelect.cpp


Index: lib/CodeGen/GlobalISel/RegBankSelect.cpp
===================================================================
--- lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -696,8 +696,21 @@
                            "unable to map instruction", MI);
         return false;
       }
+
+      // It's possible the mapping changed control flow, and moved the following
+      // instruction to a new block, so figure out the new parent.
+      if (MII != End) {
+        MachineBasicBlock *NextInstBB = MII->getParent();
+        if (NextInstBB != MBB) {
+          LLVM_DEBUG(dbgs() << "Instruction mapping changed control flow\n");
+          MBB = NextInstBB;
+          MIRBuilder.setMBB(*MBB);
+          End = MBB->end();
+        }
+      }
     }
   }
+
   OptMode = SaveOptMode;
   return false;
 }


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