[PATCH] D54093: [RISCV] Lower inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 187334.
lewis-revill added a comment.

Don't use zero register for 'J' constraint.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54093/new/

https://reviews.llvm.org/D54093

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  test/CodeGen/RISCV/inline-asm.ll

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