[PATCH] D58066: [MCA][Scheduler] Use latency information to further classify busy instructions.

[Clement Courbet via Phabricator via llvm-commits]

courbet added inline comments.
Herald added a subscriber: jdoerfert.


================
Comment at: lib/MCA/Instruction.cpp:161
   // A partial register write cannot complete before a dependent write.
-  auto IsDefReady = [&](const WriteState &Def) {
-    if (!Def.getDependentWrite()) {
-      unsigned CyclesLeft = Def.getDependentWriteCyclesLeft();
-      return !CyclesLeft || CyclesLeft < getLatency();
-    }
+  auto IsDefReady = [&](const WriteState &Def) { return Def.isReady(); };
+
----------------
the capture is no longer needed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58066/new/

https://reviews.llvm.org/D58066