[PATCH] D58066: [MCA][Scheduler] Use latency information to further classify busy instructions.
Andrea Di Biagio via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 11 10:52:02 PST 2019
andreadb created this revision.
andreadb added reviewers: mattd, RKSimon, courbet.
Herald added a subscriber: javed.absar.
This patch introduces a new instruction stage named 'IS_WAITING'.
An instruction transitions from the IS_DISPATCHED to the IS_WAITING stage if the latency of all input register operands are known.
This patch also adds a new set of instructions named 'PendingSet' to class Scheduler. The idea is that the PendingSet will only contain instructions that have reached the IS_WAITING stage.
By construction, an instruction in the PendingSet is only dependent on instructions that have already reached the execution stage. The plan is to use this knowledge to identify bottlenecks caused by data dependencies (see PR37494).
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