[llvm] r353692 - [ARM] Add v8m.base pattern for add negative imm

[Sam Parker via llvm-commits]

Author: sam_parker
Date: Mon Feb 11 03:35:42 2019
New Revision: 353692

URL: http://llvm.org/viewvc/llvm-project?rev=353692&view=rev
Log:
[ARM] Add v8m.base pattern for add negative imm

The v8m.base ISA contains movw, which can operate on an unsigned
16-bit value. Add the pattern that converts an add with a negative
value, that could fit into 16-bits when negated, into a sub with that
positive value.

Differential Revision: https://reviews.llvm.org/D57942

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/CodeGen/ARM/sub.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=353692&r1=353691&r2=353692&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Feb 11 03:35:42 2019
@@ -2147,6 +2147,11 @@ def : T2Pat<(add        GPR:$src, imm0_4
 def : T2Pat<(add        GPR:$src, imm0_65535_neg:$imm),
             (t2SUBrr    GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
 
+// Do the same for v8m targets since they support movw with a 16-bit value.
+def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm),
+             (tSUBrr tGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>,
+             Requires<[HasV8MBaseline]>;
+
 let AddedComplexity = 1 in
 def : T2Pat<(ARMaddc    rGPR:$src, imm1_255_neg:$imm),
             (t2SUBSri   rGPR:$src, imm1_255_neg:$imm)>;

Modified: llvm/trunk/test/CodeGen/ARM/sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sub.ll?rev=353692&r1=353691&r2=353692&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/sub.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/sub.ll Mon Feb 11 03:35:42 2019
@@ -1,10 +1,13 @@
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -show-mc-encoding -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
 ; RUN: llc -mtriple=armeb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
+; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=CHECK-V6M
+; RUN: llc -mtriple=thumbv8m.base -show-mc-encoding %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8M
+; RUN: llc -mtriple=thumbv8m.main -show-mc-encoding %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8M
 
 ; 171 = 0x000000ab
 define i64 @f1(i64 %a) {
-; CHECK: f1
-; CHECK-LE: subs r0, r0, #171
+; CHECK-LABEL: f1
+; CHECK-LE: subs{{.*}} r0, #171
 ; CHECK-LE: sbc r1, r1, #0
 ; CHECK-BE: subs r1, r1, #171
 ; CHECK-BE: sbc r0, r0, #0
@@ -14,8 +17,8 @@ define i64 @f1(i64 %a) {
 
 ; 66846720 = 0x03fc0000
 define i64 @f2(i64 %a) {
-; CHECK: f2
-; CHECK-LE: subs r0, r0, #66846720
+; CHECK-LABEL: f2
+; CHECK-LE: subs{{.*}} r0, r0, #66846720
 ; CHECK-LE: sbc r1, r1, #0
 ; CHECK-BE: subs r1, r1, #66846720
 ; CHECK-BE: sbc r0, r0, #0
@@ -25,8 +28,8 @@ define i64 @f2(i64 %a) {
 
 ; 734439407618 = 0x000000ab00000002
 define i64 @f3(i64 %a) {
-; CHECK: f3
-; CHECK-LE: subs r0, r0, #2
+; CHECK-LABEL: f3
+; CHECK-LE: subs{{.*}} r0, #2
 ; CHECK-LE: sbc r1, r1, #171
 ; CHECK-BE: subs r1, r1, #2
 ; CHECK-BE: sbc r0, r0, #171
@@ -36,22 +39,47 @@ define i64 @f3(i64 %a) {
 
 define i32 @f4(i32 %x) {
 entry:
-; CHECK: f4
-; CHECK: rsbs
+; CHECK-LABEL: f4
+; CHECK-LE: rsbs
+; CHECK-BE: rsbs
   %sub = sub i32 1, %x
   %cmp = icmp ugt i32 %sub, 0
   %sel = select i1 %cmp, i32 1, i32 %sub
   ret i32 %sel
 }
 
-; rdar://11726136
 define i32 @f5(i32 %x) {
 entry:
-; CHECK: f5
-; CHECK: movw r1, #65535
+; CHECK-LABEL: f5:
+; CHECK-LE:  movw r1, #65535 @ encoding: [0xff,0x1f,0x0f,0xe3]
+; CHECK-V8M: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71]
 ; CHECK-NOT: movt
 ; CHECK-NOT: add
-; CHECK: sub r0, r0, r1
+; CHECK: sub{{.*}} r0, r0, r1
+
+; CHECK-V6M-LABEL: f5
+; CHECK-V6M: ldr [[NEG:r[0-1]+]], [[CONST:.[A-Z0-9_]+]]
+; CHECK-V6M: add{{.*}} r0, [[NEG]]
+; CHECK-V6M: [[CONST]]
+; CHECK-V6M: .long   4294901761
   %sub = add i32 %x, -65535
   ret i32 %sub
 }
+
+define i32 @f6(i32 %x) {
+entry:
+; CHECK-LABEL: f6:
+; CHECK-LE:  movw r1, #65535 @ encoding: [0xff,0x1f,0x0f,0xe3]
+; CHECK-V8M: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71]
+; CHECK-NOT: movt
+; CHECK-NOT: sub
+; CHECK: add{{.*}} r0, r1
+
+; CHECK-V6M-LABEL: f6
+; CHECK-V6M: ldr [[NEG:r[0-1]+]], [[CONST:.[A-Z0-9_]+]]
+; CHECK-V6M: add{{.*}} r0, [[NEG]]
+; CHECK-V6M: [[CONST]]
+; CHECK-V6M: .long 65535
+  %sub = sub i32 %x, -65535
+  ret i32 %sub
+}