[PATCH] D55373: [LSR] Generate formulae to enable more indexed accesses

[Sam Parker via Phabricator via llvm-commits]

samparker marked 2 inline comments as done.
samparker added inline comments.


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Comment at: lib/Target/ARM/ARMTargetTransformInfo.h:97
+  bool shouldFavorBackedgeIndex(const Loop *L) const {
+    if (L->getHeader()->getParent()->optForSize())
+      return false;
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gilr wrote:
> Is this optimization inherently code-size unfriendly for ARM? (The patch actually reduces the instruction count in LSR's Cost when this optimization kicks in)
There's two reasons really: the transform is most useful in 'unrolled' loops (which we disable when optimising for code size), and this transform will introduce instructions into the preheader and if the address can't be kept in the same register, we'll also produce moves. So this is mainly a defensive restriction, because I haven't been tracking code size, but I would hope that I can remove the restriction later.


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Comment at: lib/Target/ARM/ARMTargetTransformInfo.h:99
+      return false;
+    return ST->isMClass() && ST->isThumb2() && L->getNumBlocks() == 1;
+  }
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gilr wrote:
> Is the single-block constraint due to CodeGen's single-block optimization scope? (If so, then IINM it's not target-specific)
No, its not because of ISel restrictions or anything like that. It's because the transform is only likely to be useful is the address can be kept in the same register - which becomes increasingly less likely once multiple blocks are considered.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55373/new/

https://reviews.llvm.org/D55373