[PATCH] D55373: [LSR] Generate formulae to enable more indexed accesses
Gil Rapaport via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 6 12:40:53 PST 2019
gilr added inline comments.
================
Comment at: include/llvm/Analysis/TargetTransformInfo.h:489
+ bool shouldFavorBackedgeIndex(const Loop *L) const;
+
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Please add a doxygen comment.
================
Comment at: lib/Target/ARM/ARMTargetTransformInfo.h:97
+ bool shouldFavorBackedgeIndex(const Loop *L) const {
+ if (L->getHeader()->getParent()->optForSize())
+ return false;
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Is this optimization inherently code-size unfriendly for ARM? (The patch actually reduces the instruction count in LSR's Cost when this optimization kicks in)
================
Comment at: lib/Target/ARM/ARMTargetTransformInfo.h:99
+ return false;
+ return ST->isMClass() && ST->isThumb2() && L->getNumBlocks() == 1;
+ }
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Is the single-block constraint due to CodeGen's single-block optimization scope? (If so, then IINM it's not target-specific)
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D55373/new/
https://reviews.llvm.org/D55373
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