[PATCH] D54296: [WIP, RISCV] Lower inline asm constraint A for RISC-V

[James Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

I think we should introduce a new `Constraint_A` enum member for this case. Whilst "A" currently behaves the same for the RISC-V backend as "m", that won't necessarily be the case forever. "A" is required to always be a single GPR (and so can be used for the atomic instructions, or ones with reduced immediate encoding space), but "m" (at least according to GCC) is "any kind of address that the machine supports in general", which I assume for RISC-V means reg+simm12.


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  rL LLVM

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  https://reviews.llvm.org/D54296/new/

https://reviews.llvm.org/D54296