[PATCH] D54296: [WIP, RISCV] Lower inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 185312.
lewis-revill added a comment.
Herald added a project: LLVM.

Don't output an additional '0' when printing indirect memory operands.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54296/new/

https://reviews.llvm.org/D54296

Files:
  lib/Target/RISCV/RISCVAsmPrinter.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  test/CodeGen/RISCV/inline-asm.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D54296.185312.patch
Type: text/x-patch
Size: 3616 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190205/1d142f35/attachment.bin>