[PATCH] D55341: [RISCV] Support assembling TLS add and associated modifiers

[James Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp:282
       FixupKind = RISCV::fixup_riscv_got_hi20;
       RelaxCandidate = true;
       break;
----------------
jrtc27 wrote:
> I assume this is coming from your local rebasing of my patches. Note that `GOT_HI` is *not* a relax candidate so this is incorrect.
To clarify why: HI20/LO12 and PCREL_HI20/PCREL_LO12 pairs are relaxed to use GP, CALL/CALL_PLT are relaxed to a single (C.)JAL(R), and TPREL_HI20/TPREL_ADD/TPREL_LO12 is relaxed to a single TP-relative instruction (the LUI and ADDI disappear, and the LO12's instruction's base register is changed to TP).

Since the GOT is almost certainly not within 2K of PC, there's no opportunity to shorten the sequence for PIC. In theory, if you're linking -fPIC code into an executable, you could relax the indirection via the GOT (similarly if you're using -Bsymbolic and the symbol is defined in the output), and also for an executable you could go further and apply the same GP relaxation. However, these are both fairly niche, unlike the other relaxations, hence why they don't exist.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D55341/new/

https://reviews.llvm.org/D55341