[PATCH] D55341: [RISCV] Support assembling TLS add and associated modifiers

[James Clarke via Phabricator via llvm-commits]

jrtc27 requested changes to this revision.
jrtc27 added inline comments.
This revision now requires changes to proceed.


================
Comment at: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp:147
+  Fixups.push_back(MCFixup::create(
+      0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
+
----------------
We also need a `fixup_riscv_relax` depending on `STI.getFeatureBits()[RISCV::FeatureRelax]`.


================
Comment at: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp:251
     case RISCVMCExpr::VK_RISCV_Invalid:
+    case RISCVMCExpr::VK_RISCV_TPREL_ADD:
       llvm_unreachable("Unhandled fixup kind!");
----------------
Maybe add a comment explaining why we don't expect to see it? Also, perhaps a separate `llvm_unreachable` that's more useful?


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Comment at: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp:282
       FixupKind = RISCV::fixup_riscv_got_hi20;
       RelaxCandidate = true;
       break;
----------------
I assume this is coming from your local rebasing of my patches. Note that `GOT_HI` is *not* a relax candidate so this is incorrect.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55341/new/

https://reviews.llvm.org/D55341