[llvm] r352997 - [X86][AVX] Support shuffle combining for VPMOVZX with smaller vector sources

Alina Sbirlea via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 4 17:20:08 PST 2019


FYI, this appears to have broken Halide codegen. We're seeing crashes:

PC: @     0x55573e53ff04  (unknown)  llvm::EVT::getExtendedSizeInBits()

    @     0x55573ef6057f       1664  FailureSignalHandler()

    @     0x7f1d375ca9a0  1273613376  (unknown)

    @     0x55573dd636f9       5104  combineX86ShufflesConstants()

    @     0x55573dd62fad       1456  combineX86ShufflesRecursively()

    @     0x55573dd62f51       1504  combineX86ShufflesRecursively()

    @     0x55573dd62f51       1504  combineX86ShufflesRecursively()

    @     0x55573dd23fd5       1968  combineVectorPack()

    @     0x55573dd05771       1216
llvm::X86TargetLowering::PerformDAGCombine()

    @     0x55573e28bfc1        352  (anonymous
namespace)::DAGCombiner::combine()

    @     0x55573e28a512       1424  llvm::SelectionDAG::Combine()

    @     0x55573e39bd6b        512
llvm::SelectionDAGISel::CodeGenAndEmitDAG()

    @     0x55573e39ab46        896
llvm::SelectionDAGISel::SelectAllBasicBlocks()

    @     0x55573e397ab6        208
llvm::SelectionDAGISel::runOnMachineFunction()

    @     0x55573ddc3801         32  (anonymous
namespace)::X86DAGToDAGISel::runOnMachineFunction()

    @     0x55573e18d14b       1024
llvm::MachineFunctionPass::runOnFunction()

    @     0x55573ebf9c1c        192  llvm::FPPassManager::runOnFunction()

    @     0x55573ebf9ed3         48  llvm::FPPassManager::runOnModule()

    @     0x55573ebfa3a9        352  llvm::legacy::PassManagerImpl::run()


Working to minimize a test-case.

On Sun, Feb 3, 2019 at 8:10 AM Simon Pilgrim via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: rksimon
> Date: Sun Feb  3 08:10:18 2019
> New Revision: 352997
>
> URL: http://llvm.org/viewvc/llvm-project?rev=352997&view=rev
> Log:
> [X86][AVX] Support shuffle combining for VPMOVZX with smaller vector
> sources
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>     llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=352997&r1=352996&r2=352997&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Feb  3 08:10:18 2019
> @@ -6775,13 +6775,21 @@ static bool getFauxShuffleMask(SDValue N
>    }
>    case ISD::ZERO_EXTEND_VECTOR_INREG:
>    case ISD::ZERO_EXTEND: {
> -    // TODO - add support for VPMOVZX with smaller input vector types.
>      SDValue Src = N.getOperand(0);
>      MVT SrcVT = Src.getSimpleValueType();
> -    if (NumSizeInBits != SrcVT.getSizeInBits())
> -      break;
> -    DecodeZeroExtendMask(SrcVT.getScalarSizeInBits(), NumBitsPerElt,
> NumElts,
> -                         Mask);
> +    unsigned NumSrcBitsPerElt = SrcVT.getScalarSizeInBits();
> +    DecodeZeroExtendMask(NumSrcBitsPerElt, NumBitsPerElt, NumElts, Mask);
> +
> +    if (NumSizeInBits != SrcVT.getSizeInBits()) {
> +      assert((NumSizeInBits % SrcVT.getSizeInBits()) == 0 &&
> +             "Illegal zero-extension type");
> +      SrcVT = MVT::getVectorVT(SrcVT.getScalarType(),
> +                               NumSizeInBits / NumSrcBitsPerElt);
> +      Src = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), SrcVT,
> +                        DAG.getUNDEF(SrcVT), Src,
> +                        DAG.getIntPtrConstant(0, SDLoc(N)));
> +    }
> +
>      Ops.push_back(Src);
>      return true;
>    }
>
> Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll?rev=352997&r1=352996&r2=352997&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v8.ll Sun Feb  3
> 08:10:18 2019
> @@ -1526,9 +1526,8 @@ define <8 x i32> @shuffle_v8i32_08192a3b
>  ;
>  ; AVX512VL-LABEL: shuffle_v8i32_08192a3b:
>  ; AVX512VL:       # %bb.0:
> -; AVX512VL-NEXT:    vpmovzxdq {{.*#+}} ymm2 =
> xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
> -; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm0 = [0,8,2,9,4,10,6,11]
> -; AVX512VL-NEXT:    vpermi2d %ymm1, %ymm2, %ymm0
> +; AVX512VL-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,8,1,9,2,10,3,11]
> +; AVX512VL-NEXT:    vpermt2d %ymm1, %ymm2, %ymm0
>  ; AVX512VL-NEXT:    retq
>    %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0,
> i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
>    ret <8 x i32> %shuffle
> @@ -1572,11 +1571,23 @@ define <8 x i32> @shuffle_v8i32_091b2d3f
>  ; AVX1-NEXT:    vblendps {{.*#+}} ymm0 =
> ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
>  ; AVX1-NEXT:    retq
>  ;
> -; AVX2OR512VL-LABEL: shuffle_v8i32_091b2d3f:
> -; AVX2OR512VL:       # %bb.0:
> -; AVX2OR512VL-NEXT:    vpmovzxdq {{.*#+}} ymm0 =
> xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
> -; AVX2OR512VL-NEXT:    vpblendd {{.*#+}} ymm0 =
> ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
> -; AVX2OR512VL-NEXT:    retq
> +; AVX2-LABEL: shuffle_v8i32_091b2d3f:
> +; AVX2:       # %bb.0:
> +; AVX2-NEXT:    vpmovzxdq {{.*#+}} ymm0 =
> xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
> +; AVX2-NEXT:    vpblendd {{.*#+}} ymm0 =
> ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
> +; AVX2-NEXT:    retq
> +;
> +; AVX512VL-SLOW-LABEL: shuffle_v8i32_091b2d3f:
> +; AVX512VL-SLOW:       # %bb.0:
> +; AVX512VL-SLOW-NEXT:    vpmovzxdq {{.*#+}} ymm0 =
> xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
> +; AVX512VL-SLOW-NEXT:    vpblendd {{.*#+}} ymm0 =
> ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
> +; AVX512VL-SLOW-NEXT:    retq
> +;
> +; AVX512VL-FAST-LABEL: shuffle_v8i32_091b2d3f:
> +; AVX512VL-FAST:       # %bb.0:
> +; AVX512VL-FAST-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,9,1,11,2,13,3,15]
> +; AVX512VL-FAST-NEXT:    vpermt2d %ymm1, %ymm2, %ymm0
> +; AVX512VL-FAST-NEXT:    retq
>    %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0,
> i32 9, i32 1, i32 11, i32 2, i32 13, i32 3, i32 15>
>    ret <8 x i32> %shuffle
>  }
>
>
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