[PATCH] D56864: [x86] vectorize cast ops in lowering to avoid register file transfers

[Sanjay Patel via Phabricator via llvm-commits]

spatel marked an inline comment as done.
spatel added inline comments.


================
Comment at: test/CodeGen/X86/vec_int_to_fp.ll:5581
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vmovd %xmm0, %eax
-; AVX-NEXT:    vcvtsi2sdl %eax, %xmm1, %xmm0
+; AVX-NEXT:    vcvtdq2pd %xmm0, %xmm0
 ; AVX-NEXT:    retq
----------------
spatel wrote:
> We miss this with SSE because the v4f64 type is not legal. We need to add another check to allow conversion to v2f64 directly if we're extracting from the zero or low elements of a 128-bit source vector.
I have an ugly draft of a patch that would handle that case. It requires that we produce a X86ISD::CVTSI2P node rather than the generic SINT_TO_FP and that we return/adjust the destination type rather than assuming it's a vector with the same number of elements.

I'd prefer to do that in a follow-up commit to reduce risk (assuming we're ok with this general direction).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56864/new/

https://reviews.llvm.org/D56864