[PATCH] D56864: [x86] vectorize cast ops in lowering to avoid register file transfers

[Sanjay Patel via Phabricator via llvm-commits]

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In D56864#1365597 <https://reviews.llvm.org/D56864#1365597>, @RKSimon wrote:

> Do we have a SSE2/AVX1 cvtdq2pd test case?


See inline comment for 'vec_int_to_fp.ll: extract0_sitofp_v4i32_f64().' Let me know if you're thinking of a different pattern.



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Comment at: test/CodeGen/X86/vec_int_to_fp.ll:5581
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vmovd %xmm0, %eax
-; AVX-NEXT:    vcvtsi2sdl %eax, %xmm1, %xmm0
+; AVX-NEXT:    vcvtdq2pd %xmm0, %xmm0
 ; AVX-NEXT:    retq
----------------
We miss this with SSE because the v4f64 type is not legal. We need to add another check to allow conversion to v2f64 directly if we're extracting from the zero or low elements of a 128-bit source vector.


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