[PATCH] D57141: [RISCV][WIP] Add implied zero offset load/store alias pattern

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


================
Comment at: lib/Target/RISCV/RISCVInstrInfo.td:538
+
+def : InstAlias<"lw  $rd, (${rs1})", (LW   GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"lwu $rd, (${rs1})", (LWU  GPR:$rd,  GPR:$rs1,     0), 0>;
----------------
LW should not be guarded by `IsRV64`.


================
Comment at: lib/Target/RISCV/RISCVInstrInfo.td:541
+def : InstAlias<"sd $rs2, (${rs1})", (SD   GPR:$rs2, GPR:$rs1,     0), 0>;
+
 } // Predicates = [IsRV64]
----------------
LD is missing here.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57141/new/

https://reviews.llvm.org/D57141