[PATCH] D57141: [RISCV][WIP] Add implied zero offset load/store alias pattern

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos.
Herald added subscribers: llvm-commits, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar.

Allow load/store instruction with implied zero offset, for compatible with GNU assembler.


Repository:
  rL LLVM

https://reviews.llvm.org/D57141

Files:
  lib/Target/RISCV/RISCVInstrInfo.td


Index: lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.td
+++ lib/Target/RISCV/RISCVInstrInfo.td
@@ -521,10 +521,24 @@
 def PseudoSH  : PseudoStore<"sh">;
 def PseudoSW  : PseudoStore<"sw">;
 
+def : InstAlias<"lb  $rd, (${rs1})", (LB   GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"lbu $rd, (${rs1})", (LBU  GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"lh  $rd, (${rs1})", (LH   GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"lhu $rd, (${rs1})", (LHU  GPR:$rd,  GPR:$rs1,     0), 0>;
+
+def : InstAlias<"sb $rs2, (${rs1})", (SB  GPR:$rs2,  GPR:$rs1,     0), 0>;
+def : InstAlias<"sh $rs2, (${rs1})", (SH  GPR:$rs2,  GPR:$rs1,     0), 0>;
+def : InstAlias<"sw $rs2, (${rs1})", (SW  GPR:$rs2,  GPR:$rs1,     0), 0>;
+
 let Predicates = [IsRV64] in {
 def PseudoLWU : PseudoLoad<"lwu">;
 def PseudoLD  : PseudoLoad<"ld">;
 def PseudoSD  : PseudoStore<"sd">;
+
+def : InstAlias<"lw  $rd, (${rs1})", (LW   GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"lwu $rd, (${rs1})", (LWU  GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"sd $rs2, (${rs1})", (SD   GPR:$rs2, GPR:$rs1,     0), 0>;
+
 } // Predicates = [IsRV64]
 
 def : InstAlias<"mv $rd, $rs",   (ADDI GPR:$rd, GPR:$rs,       0)>;


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