[PATCH] D57085: [RISCV] Custom-legalise 32-bit variable shifts on RV64

[Alex Bradbury via Phabricator via llvm-commits]

asb marked an inline comment as done.
asb added inline comments.


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Comment at: lib/Target/RISCV/RISCVISelLowering.h:37
+  SRAW,
+  SRLW
 };
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efriedma wrote:
> Probably worth explicitly noting whether the shift amount is modulo.  If it is, you might want to implement SimplifyDemandedBitsForTargetNode.
Yes, only the lower 5 bits are used. Thanks for the tip re SimplifyDemandedBitsForTargetNode. I had hoped that would allow me to remove the patterns that match a masked shamt, as the DAG combiner will remove the mask instead. This works for the test cases with a sign-extended or zero-extended result, but not anyext as SimplifyDemandedBits is never called. 

I'm not entirely sure what the best behaviour is here:
* Leaving as-is
* Leaving a pattern to handle the anyext case but adding SimplifyDemandedBitsForTargetNode
* Adding a target DAG combine that calls SimplifyDemandedBits on the Shamt.


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  https://reviews.llvm.org/D57085/new/

https://reviews.llvm.org/D57085