[PATCH] D57085: [RISCV] Custom-legalise 32-bit variable shifts on RV64

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: lib/Target/RISCV/RISCVISelLowering.h:37
+  SRAW,
+  SRLW
 };
----------------
Probably worth explicitly noting whether the shift amount is modulo.  If it is, you might want to implement SimplifyDemandedBitsForTargetNode.


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  https://reviews.llvm.org/D57085/new/

https://reviews.llvm.org/D57085