[PATCH] D56387: [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: test/CodeGen/ARM/lowerMUL-newload.ll:28
 ; CHECK-NEXT:    bx lr
 entry:
 ; The test case trying to vectorize the pseudo code below.
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huihuiz wrote:
> RKSimon wrote:
> > This just looks like we're missing something for the ARMISD::VMULL lowering
> Using "CHECK-NEXT" and matching with the exact register names will make this test cast very sensitive to scheduling and register allocation changes.
> Use pattern matching should be a better approach.
But it stops people missing/hiding codegen changes that need to be kept an eye on, including register allocation changes.

This argument has been going on for years now, and we've tended to see that the benefits of update_llc_test_checks.py outweighs any difficulties.

More importantly, do you have any insights as to how to improve ARMISD::VMULL lowering?


Repository:
  rL LLVM

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  https://reviews.llvm.org/D56387/new/

https://reviews.llvm.org/D56387