[PATCH] D56387: [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (WIP)

[Huihui Zhang via Phabricator via llvm-commits]

huihuiz added inline comments.


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Comment at: test/CodeGen/ARM/lowerMUL-newload.ll:28
 ; CHECK-NEXT:    bx lr
 entry:
 ; The test case trying to vectorize the pseudo code below.
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RKSimon wrote:
> This just looks like we're missing something for the ARMISD::VMULL lowering
Using "CHECK-NEXT" and matching with the exact register names will make this test cast very sensitive to scheduling and register allocation changes.
Use pattern matching should be a better approach.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D56387/new/

https://reviews.llvm.org/D56387