[PATCH] D57096: [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Adding target-specific nodes for this is a little unfortunate, but seems reasonable.



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Comment at: lib/Target/RISCV/RISCVInstrInfoM.td:66
+          (DIVW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(sext_inreg (riscv_divw GPR:$rs1, GPR:$rs2), i32),
           (DIVW GPR:$rs1, GPR:$rs2)>;
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Since you have a custom DAG node, you might as well implement ComputeNumSignBitsForTargetNode instead of using a pattern like this.


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  https://reviews.llvm.org/D57096/new/

https://reviews.llvm.org/D57096