[PATCH] D57044: [AArch64] Optimize Inf materialization
Adhemerval Zanella via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 23 09:54:22 PST 2019
zatrazz marked an inline comment as done.
zatrazz added inline comments.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5430
+ // We can materialize #0.0 and #INF as fmov $Rd, XZR for 64-bit and 32-bit
+ // cases.
// FIXME: We should be able to handle f128 as well with a clever lowering.
----------------
efriedma wrote:
> This comment is wrong.
What about:
// We can materialize #0.0 as fmov $Rd, XZR and #INF as orr $Rx, XZR, CTE
// plus fmov $Rd for 64-bit and 32-bit cases.
?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D57044/new/
https://reviews.llvm.org/D57044
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