[PATCH] D57056: [MC][X86] Correctly model additional operand latency caused by transfer delays from the integer to the floating point unit.

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL351965: [MC][X86] Correctly model additional operand latency caused by transfer delays… (authored by adibiagio, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D57056?vs=183088&id=183107#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57056/new/

https://reviews.llvm.org/D57056

Files:
  llvm/trunk/include/llvm/MC/MCSchedule.h
  llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
  llvm/trunk/include/llvm/MCA/Instruction.h
  llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp
  llvm/trunk/lib/MC/MCSchedule.cpp
  llvm/trunk/lib/MCA/InstrBuilder.cpp
  llvm/trunk/lib/Target/X86/X86InstrMMX.td
  llvm/trunk/lib/Target/X86/X86InstrSSE.td
  llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
  llvm/trunk/lib/Target/X86/X86SchedHaswell.td
  llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
  llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/trunk/lib/Target/X86/X86Schedule.td
  llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
  llvm/trunk/lib/Target/X86/X86ScheduleBdVer2.td
  llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
  llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
  llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
  llvm/trunk/test/CodeGen/X86/mmx-schedule.ll
  llvm/trunk/test/CodeGen/X86/sse41-schedule.ll
  llvm/trunk/test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-1.s
  llvm/trunk/test/tools/llvm-mca/X86/BtVer2/int-to-fpu-forwarding-3.s
  llvm/trunk/tools/llvm-mca/Views/InstructionInfoView.cpp

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